Minimizing power is the number one priority in semiconductor design today. Managing power throughout the design process, from architectural definition to tapeout, is critical especially with System-on-Chip designs comprising hundreds of millions of transistors, interconnects, and routing lines.
Power density (mW/sq. cm) is another critical parameter which when exceeding certain level, results in localized hot spots which may affect chip performance and reliability.
Every design is characterized by its speed (frequency) and energy used to achieve desired performance. Finding the optimal design point in the Energy–Delay space is critical in designing a competitive product. Silicon Analytic’s pTunerTM is the tool that will bring this design point closest to the physical limits, i.e. the lowest achievable power at the highest possible frequency. The tool also allows the designer to make critical decisions during the design process that would result in a competitive design, optimized for the given application.
- o is a new EDA tool, that is not available as a part of the standard CAD tool suites provided by the major EDA vendors.
- o provides best-in-breed power results, with minimal CPU runtime.
- o does not require any deviations from the existing design flow. The tool integrates seamlessly into current design methodologies as a plug in to leading EDA tools.